Multiple instruction set architectures on a processing device

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12260219
APP PUB NO 20240036866A1
SERIAL NO

18355939

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Abstract

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Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

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Patent Owner(s)

Patent OwnerAddress
TEXAS INSTRUMENTS INCORPORATEDPO BOX 655474 MS 3999 DALLAS TX 75265

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Anderson, Timothy D University Park, US 137 1170
Bui, Duc Grand Prairie, US 49 80
Gauvreau, Paul Richardson, US 3 6

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