Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12260165
APP PUB NO 20240037314A1
SERIAL NO

18378384

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Abstract

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Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.

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Patent Owner(s)

Patent OwnerAddress
MYTHIC INC1905-A KRAMER LN SUITE 200 AUSTIN TX 78758

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dang-Tran, Alexander Austin, US 4 7
Fick, David Cedar Park, US 41 127
Iyer, Balaji Austin, US 6 64
Morten, Andrew Cupertino, US 15 26
Romano, Anthony Austin, US 38 807
Stotzer, Eric Austin, US 8 64
Wu, Pei-Ci Millbrae, US 11 19

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