Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture
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United States of America
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Mar 25, 2025
Grant Date -
Feb 1, 2024
app pub date -
Oct 10, 2023
filing date -
Oct 10, 2023
priority date (Note) -
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status (Latency Note)
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Abstract
Systems and methods for optimizing data flow in an integrated circuit includes creating a task graph based on transforming an optimized network graph for a neural network application, wherein creating the task graph includes: enumerating a plurality of distinct tasks based on a decomposition of each of a plurality of network operations of the optimized network graph; and allocating a data buffer to each of pairs of dependent tasks of the plurality of distinct tasks based on the decomposition of each of the plurality of network operations of the optimized network graph; encoding a token-informed task scheduler based on a composition of the task graph, wherein the encoding the token-informed task scheduler includes: programming the token-informed task scheduler to cause an execution of the plurality of distinct tasks based on identifying a state of a respective data buffer between each of the pairs of dependent tasks.
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International Classification(s)
- 2023 Application Filing Year
- G06N Class
- 9892 Applications Filed
- 2446 Patents Issued To-Date
- 24.73 % Issued To-Date
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Patent Citation Ranking
- 0 Citation Count
- G06N Class
- 0 % this patent is cited more than
- < 1 Age
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