Architecture for managing asynchronous resets in a system-on-a-chip
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United States of America
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Mar 25, 2025
Grant Date -
Jun 13, 2024
app pub date -
May 11, 2023
filing date -
May 11, 2023
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Abstract
Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.
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