Memory device, semiconductor device, and method of fabricating semiconductor device
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United States of America
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Mar 18, 2025
Grant Date -
Oct 12, 2023
app pub date -
Jun 12, 2023
filing date -
Jun 12, 2023
priority date (Note) -
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Abstract
A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.
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