Clock monitor
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
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Mar 18, 2025
Grant Date -
Dec 22, 2022
app pub date -
Jun 10, 2021
filing date -
Jun 10, 2021
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A clock monitor circuit detects departures from expected values for clock period, clock high time duration, or clock low time duration. A delay line of the clock monitor circuit is composed of delay portions of delay cells. Each delay cell also has a comparator portion with logic to compare aspects of the monitored clock signal to corresponding expected values, and to output a failure detection signal indicating whether the expected values are met. Expected values may be read from a fuse set. The delay of the delay line may be programmatically adjusted. The clock monitor circuit may be combined with a circuit that detects narrow glitches in the monitored clock signal. Devices and systems with one or more monitored clock signals, and methods of clock signal monitoring, are also described.
First Claim
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Family
Country | kind | publication No. | Filing Date | Type | Sub-Type |
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- MICROSOFT TECHNOLOGY LICENSING, LLC.
International Classification(s)

- 2021 Application Filing Year
- H03K Class
- 2358 Applications Filed
- 1507 Patents Issued To-Date
- 63.92 % Issued To-Date
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Fiedler, Alan Scott | Santa Barbara, US | 1 | 4 |
# of filed Patents : 1 Total Citations : 4 |
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- H03K Class
- 0 % this patent is cited more than
- < 1 Age
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