Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof
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United States of America
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Mar 18, 2025
Grant Date -
May 9, 2024
app pub date -
Jan 15, 2024
filing date -
Jan 15, 2024
priority date (Note) -
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Abstract
A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit coupled between the current control circuit and a ground. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. First terminals of the first transistors each is in connection with one of the bit lines. Second terminals of the first transistors each is in connection with the discharge enable circuit. Third terminals of the first transistors are in connection with a reference current generator of the current control circuit.
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