Memory device including page buffer, memory system including page buffer, and operating method thereof
Number of patents in Portfolio can not be more than 2000
United States of America
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Mar 18, 2025
Grant Date -
Jul 18, 2024
app pub date -
Feb 23, 2023
filing date -
Feb 23, 2023
priority date (Note) -
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Abstract
The present disclosure provides a memory device that includes a memory array and a page buffer. The memory array includes a plurality of memory cells coupled to a bit line of the memory array. The page buffer is coupled to the plurality of memory cells via the bit line to sense stored data in the memory cells. The page buffer includes first, second, and third transistors coupled to the bit line, first and second nodes, a capacitance structure coupled to the first node, and a latch circuit coupled to the bit line via the first transistor. First terminals of the first, second, and third transistors are coupled to the first node. A second terminal of the second transistor is coupled to the second node. The third transistor amplifies a read margin voltage at the second node. The page buffer shortens a time of a read operation or verify operation.
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