Memory device
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United States of America
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Mar 18, 2025
Grant Date -
Nov 14, 2024
app pub date -
May 9, 2023
filing date -
May 9, 2023
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Abstract
A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.
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