Signal detection system for duty cycle testing and memory detection method
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United States of America
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Mar 18, 2025
Grant Date -
Jan 19, 2023
app pub date -
Sep 29, 2022
filing date -
Sep 29, 2022
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Abstract
A signal detection system and a memory detection method are provided. The system includes a signal generator, generating a reference test signal based on an external parameter, the reference test signal being a clock signal satisfying a preset duty cycle, where a duty cycle test is performed on the reference test signal based on a test circuit, to determine whether a function of the test circuit is normal. If the function of the test circuit is normal, different portions under test are sequentially selected based on a test control signal, and the duty cycle test is performed, based on the test circuit, on a signal outputted by each of the selected portions under test. The portions under test include a signal converter and a write clock path.
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