Test circuit, test method and memory
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United States of America
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Mar 18, 2025
Grant Date -
Jan 19, 2023
app pub date -
Sep 29, 2022
filing date -
Sep 29, 2022
priority date (Note) -
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Abstract
A test circuit includes first integration circuit configured to receive first test signal and integrate first test signal to output first integrated signal; second integration circuit configured to receive second test signal and integrate second test signal to output second integrated signal, where first test signal and second test signal are signals inverted with respect to each other, value of first integrated signal is product of duty cycle of first test signal and a voltage amplitude of power supply, and value of second integrated signal is product of duty cycle of second test signal and voltage amplitude of power supply; and comparison circuit connected to first and second integration circuits. The comparison circuit is configured to output high-level signal in response to first integrated signal being greater than second integrated signal, and output low-level signal in response to second integrated signal being greater than first integrated signal.
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