Memory structure and memory device

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12254939
APP PUB NO 20240194286A1
SERIAL NO

17908477

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Abstract

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A memory structure of an integrated circuit includes a plurality of memory arrays arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, the odd-numbered sensitivity amplifier array is connected to an odd-numbered global signal line, and the even-numbered sensitivity amplifier array is connected to the even-numbered global signal line; a first sensitivity amplifier array is arranged between the memory arrays at the edge, and the first sensitivity amplifier array is connected to both the odd-numbered global signal line and the even-numbered global signal line. The present disclosure can improve reliability, yield and test success rate of the memory products.

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Patent Owner(s)

  • CHANGXIN MEMORY TECHNOLOGIES, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Li, Hongwen Hefei, CN 42 236
Shang, Weibing Hefei, CN 52 34

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