Calibration method for emulating group III-V semiconductor device and method for manufacturing group III-V semiconductor device

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United States of America

PATENT NO 12254262
APP PUB NO 20230066030A1
SERIAL NO

17462747

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Abstract

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A calibration method for emulating a Group III-V semiconductor device, a method for determining trap location within a Group III-V semiconductor device and method for manufacturing a Group III-V semiconductor device are provided. Actual tape-out is performed according to an actual process flow of the Group III-V semiconductor device for manufacturing the Group III-V semiconductor devices and PCM Group III-V semiconductor device. Actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are obtained and the actual electrical performances of the Group III-V semiconductor devices and the PCM Group III-V semiconductor device are compared to determine locations where one or more traps appear.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chia-Chung Keelung, TW 115 486
Chen, Chu Fu Hsinchu County, TW 21 21
Fu, Shufang Hsinchu County, TW 1 0
Hsu, Chiao-Chun Hsinchu, TW 15 15
Huang, Chi-Feng Hsinchu County, TW 475 1797
Liu, Kuan-Hung Hsinchu, TW 26 184
Shih, Fu-Yu Hsinchu, TW 1 0

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