System for address mapping and translation protection

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12253958
APP PUB NO 20220027287A1
SERIAL NO

17496327

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ATTORNEY / AGENT: (SPONSORED)

Importance

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Abstract

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This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

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First Claim

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Patent Owner(s)

  • INTEL CORP.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Anderson, Andrew V Forest Grove, US 125 4824
Cihula, Joseph F Hillsboro, US 19 1173
Durham, David M Beaverton, US 311 6124
Gupta, Deepak K Hillsboro, US 27 178
Huntley, Barry E Hillsboro, US 128 1292
Koufaty, David A Portland, US 49 996
Lemay, Michael Hillsboro, US 127 1768
Mallick, Asit K Saratoga, US 27 314
Neiger, Gilbert Portland, US 300 7500
Patel, Baiju V Portland, US 85 2062
Sahita, Ravi L Portland, US 176 2896
Shanbhogue, Vedvyas Austin, US 230 2565
Thiyagarajah, Arumugam Folson, US 12 80

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