Software-defined coherent caching of pooled memory

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United States of America

PATENT NO 12253948
APP PUB NO 20210064531A1
SERIAL NO

17092803

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Abstract

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Methods and apparatus for software-defined coherent caching of pooled memory. The pooled memory is implemented in an environment having a disaggregated architecture where compute resources such as compute platforms are connected to disaggregated memory via a network or fabric. Software-defined caching policies are implemented in hardware in a processor SoC or discrete device such as a Network Interface Controller (NIC) by programming logic in an FPGA or accelerator on the SoC or discrete device. The programmed logic is configured to implement software-defined caching policies in hardware for effecting disaggregated memory (DM) caching in an associated DM cache of at least a portion of an address space allocated for the software application in the disaggregated memory. In connection with DM cache operations, such as cache lines evicted from a CPU, logic implemented in hardware determines whether a cache line in a DM cache is to be evicted and implements the software-defined caching policy for the DM cache including associated memory coherency operations.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bachmutsky, Alexander Sunnyvale, US 77 981
Guim, Bernat Francesc Barcelona, ES 474 2775
Kumar, Karthik Chandler, US 268 1895
Lu, Zhongyan Beijing, CN 10 50
Willhalm, Thomas Sandhausen, DE 139 1038

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