Method for programming an FPGA

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12253876
APP PUB NO 20230418324A1
SERIAL NO

18209558

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Abstract

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A method for programming an FPGA, wherein a library with elementary operations and a respective latency table for each of the elementary operations of the library are provided. a data path is defined. The latencies are recorded for a multiplicity of clock rates that are different from one another and these latencies are added for every clock rate so that a total latency for the data path results for this multiplicity of different clock rates. The ratio between the lowest total latency and the total latency at a respective clock rate is determined. A utilization of the FPGA for each clock rate is identified. The ratio between the lowest utilization of the FPGA and the utilization of the FPGA at a respective clock rate is determined. A quality factor for each clock rate while taking into account the total latency and the utilization of the FPGA is determined.

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Patent Owner(s)

  • DSPACE GMBH

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kalte, Heiko Paderborn, DE 32 30
Lubeley, Dominik Paderborn, DE 28 8

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