Clock generator circuit for near field communication device
Number of patents in Portfolio can not be more than 2000
United States of America
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Mar 11, 2025
Grant Date -
Jan 11, 2024
app pub date -
Jun 30, 2023
filing date -
Jun 30, 2023
priority date (Note) -
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Abstract
A clock generator circuit includes an oscillator circuit coupled to a bias circuit. The bias circuit includes a current mirror, third and fourth transistors, and a cascode transistor. The current mirror includes a reference transistor and a set of copy transistors that are programmable. The third transistor has a source connected to a cold spot, a drain and a gate connected to this drain. The fourth transistor has a source connected to the drain of the third transistor, a drain, and a gate connected to that drain. The cascode transistor has a source connected to a drain of at least one of the copy transistors, a drain, and a gate connected to the gate of the fourth transistor. The gates of the fourth transistor and the cascode transistor are thicker than the gates of the reference transistor, each copy transistor, and the third transistor.
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