Four-phase clock buffer of twenty-five percent duty cycle

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12249989
APP PUB NO 20250070762A1
SERIAL NO

18455676

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Abstract

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A two-stage 4-phase clock buffer having a cascade of a first stage and a second stage, wherein: the first stage includes four p-channel oxide semiconductor transistors (PMOSTs) configured in a common-source ring topology to dispatch a first 4-phase clock, and four n-channel oxide semiconductor transistors (NMOSTs) configured in a common-source topology to control the first 4-phase clock in response to a second 4-phase clock; and, the second stage includes four NMOS transistors configured in a common-source ring topology to dispatch a third 4-phase clock, and four PMOS transistors configured in a common-source topology to control the third 4-phase clock in response to the first 4-phase clock.

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Patent Owner(s)

Patent OwnerAddress
REALTEK SEMICONDUCTOR CORPHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lin, Chia-Liang (Leon) Fremont, US 121 172

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