Memory systems with vertical integration

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12249390
APP PUB NO 20230282247A1
SERIAL NO

18316743

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Abstract

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A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Jen-Yuan Hsinchu, TW 175 215
Huang, Chia-En Xinfeng Township, TW 320 426
Lee, Chieh Hsinchu, TW 51 61
Liu, Yi-Ching Hsinchu, TW 94 407
Wang, Yih Hsinchu, TW 285 868

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