Adder circuit using lookup tables

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12248764
APP PUB NO 20240281212A1
SERIAL NO

18588604

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Abstract

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A four-input lookup table (“LUT4”) is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

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Patent Owner(s)

  • ACHRONIX SEMICONDUCTOR CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ekanayake, Virantha N Baltimore, US 4 1
LaFrieda, Christopher C Ridgefield, US 7 1

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