Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable latency

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United States of America

PATENT NO 12248761
APP PUB NO 20240329924A1
SERIAL NO

18129762

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Abstract

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Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.

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Patent Owner(s)

  • XILINX INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cory, Warren E Redwood City, US 22 301
Remla, Riyas Noorudeen Singapore, SG 10 23

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