Die-to-die dynamic clock and power gating

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12248350
APP PUB NO 20230214350A1
SERIAL NO

18174985

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Abstract

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A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Davidov, Dany Tirat Carmel, IL 7 1
Ramadan, Misbah Haifa, IL 3 2
Rozen, Itamar Givat Ela, IL 2 0
Zemer, Tzach Megadim, IL 10 8

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