Dynamic power management for on-chip memory

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12243622
APP PUB NO 20240055035A1
SERIAL NO

17885753

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Abstract

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Dynamic power management for an on-chip memory, such as a system cache memory as well as other memories, is provided. The memory includes wordline sections, input/output (I/O) circuitry, and control circuitry. Each wordline section includes a number of wordlines, and each wordline section is coupled to a different wordline control circuitry. The control circuitry is configured to, in response to receiving an access request including an address, decode the address including determine, based on the address, an associated wordline, and determine, based on the associated wordline, an associated wordline section. The control circuitry is further configured to apply power to wordline control circuitry coupled to the associated wordline section.

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Patent Owner(s)

  • ARM LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
McCombs,, Jr Edward Martin Austin, US 11 12

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