Memory array structure
Number of patents in Portfolio can not be more than 2000
United States of America
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Mar 4, 2025
Grant Date -
Jan 18, 2024
app pub date -
Jul 12, 2022
filing date -
Jul 12, 2022
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Abstract
In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.
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