Read clock start and stop for synchronous memories
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United States of America
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Mar 4, 2025
Grant Date -
Apr 11, 2024
app pub date -
Dec 20, 2023
filing date -
Dec 20, 2023
priority date (Note) -
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Abstract
A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.
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