Integrated circuit margin measurement for structural testing

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12241933
APP PUB NO 20230258719A1
SERIAL NO

18014642

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Abstract

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Structural testing of a semiconductor integrated circuit (IC), including scanning test patterns or test conditions into internal circuits of the semiconductor IC, for example from a tester device. A timing margin may be measured during the structural test. The margin is measured based on a characteristic of a comparison between a test signal path of the semiconductor IC and a delayed signal path, the delayed signal path being a signal of the test signal path delayed by a variable delay time. An output of the margin measurement sensor may be scanned out, for instance to the tester device.

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Patent Owner(s)

  • PROTEANTECS LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cohen, Shai Haifa, IL 50 432
Fayneh, Eyal Givatayim, IL 64 327
Khazin, Alex Nesher, IL 5 4
Landman, Evelyn Haifa, IL 39 110

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