Delay locked loop and memory
Number of patents in Portfolio can not be more than 2000
United States of America
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Feb 25, 2025
Grant Date -
Feb 22, 2024
app pub date -
Aug 13, 2023
filing date -
Aug 13, 2023
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Abstract
A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.
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