Vertical interconnects with variable pitch for scalable escape routing
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United States of America
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Feb 25, 2025
Grant Date -
Apr 28, 2022
app pub date -
Oct 12, 2021
filing date -
Oct 12, 2021
priority date (Note) -
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Abstract
The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.
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