Low-power static random access memory
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United States of America
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Feb 25, 2025
Grant Date -
Jan 18, 2024
app pub date -
Jun 21, 2022
filing date -
Jun 21, 2022
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Abstract
A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.
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