Modular, extensible computer processing architecture
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United States of America
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Feb 25, 2025
Grant Date -
Jun 17, 2021
app pub date -
Dec 8, 2020
filing date -
Dec 8, 2020
priority date (Note) -
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status (Latency Note)
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Abstract
One aspect of the invention provides a computer processing architecture including: a plurality of processors, each processor configured to: receive a set of data from one or more input channels or from another processor; execute at least one of a plurality of individualized processes on the data; and output the processed data according to an independent clock domain of the processor; a plurality of switches, wherein each switch connects a processor to an input channel of the one or more input channels or to another processor; and a micro-controller configured to: receive the processed data; control the plurality of switches by activating or deactivating each switch; generate a pipeline of processors from activating and deactivating the plurality of switches; and select one or more individualized processes of the plurality of individualized processes that each processor within the pipeline executes.
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