Analog-to-digital converter (ADC) with reference ADC path receiving attenuated input to generate error codes for second and third harmonics by counting negative and positive codes

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United States of America

PATENT NO 12231138
APP PUB NO 20240413831A1
SERIAL NO

18206203

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Abstract

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An interleaved Analog-to-Digital Converter (ADC) has a reference channel receiving an attenuated analog input. The reference channel is also calibrated to remove capacitor-ratio mismatch, static, and dynamic mismatches and produces a linear replica of the data channels with negligible nonlinear errors due to attenuation. Nonlinear errors on the data channels are corrected by Harmonic Distortion HD2 and HD3 coefficients. A counter increments when the sign bit of a nonlinear-corrected channel code is negative. The count is doubled and reduced by a number of samples to generate a HD2 cost function that adjusts the HD2 coefficient in a LMS loop. A HD3 correlation is generated by multiplying the reference channel output by its difference with the nonlinear-corrected channel code. The sign of the correlation code increments a second counter which generates a HD3 cost function whose sign bit adjusts the HD3 coefficient. These 2 counters generate cost functions, eliminating sample storage.

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Patent Owner(s)

  • CAELUS TECHNOLOGIES LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lok, Chi Fung Hong Kong, HK 10 39

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