Self-referenced delay cell-based time-to-digital converter
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United States of America
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Feb 18, 2025
Grant Date -
Aug 31, 2023
app pub date -
May 9, 2023
filing date -
May 9, 2023
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Abstract
A time-to-digital converter (TDC) circuit includes self-referenced delay cell circuits each including: a first inverter coupled with a second inverter, the first inverter receiving a positive time signal representative of an incoming up signal; a third inverter coupled with a fourth inverter, the third inverter receiving a negative time signal representative of an incoming down signal; a first bank of capacitors coupled to a first node between the first/second inverters; and a second bank of capacitors coupled to a second node between the third/fourth inverters. Control logic generates first control signals, each with an up value, to selectively control the first bank of capacitors. Control logic generates second control signals, each with a down value, to selectively control the second bank of capacitors. The up values vary relative to the down values across the first control signals and the second control signals.
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