Systems and methods for PLL duty cycle calibration
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United States of America
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Feb 18, 2025
Grant Date -
Sep 19, 2024
app pub date -
Mar 13, 2023
filing date -
Mar 13, 2023
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status (Latency Note)
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Abstract
To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.
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International Classification(s)
- 2023 Application Filing Year
- H03L Class
- 302 Applications Filed
- 126 Patents Issued To-Date
- 41.73 % Issued To-Date
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