Multiple transistor LNA MMIC design
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United States of America
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Feb 18, 2025
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N/A
app pub date -
May 17, 2021
filing date -
May 17, 2021
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Abstract
The present disclosure is directed to low noise amplifiers built as a monolithic millimeter or microwave integrated circuit (MMIC) that includes an amplification stage with two or more field effect transistors (FETS) connected in a parallel configuration. An amplifier may include two, three, or more amplification stages. Amplifiers consistent with the present disclosure may operate at frequencies in the range of 3 gigahertz (GHz) to 9 GHz. Each transistor or amplification stage may include their own series feedback element. A second amplification stage may include two parallel transistors, with one having a series feedback element and a feedback shunt spanning the second stage. A third stage may include a single transistor. Each of the transistors connected in a parallel configuration may be tuned to a different corner frequency in order to improve metrics of noise figure, gain, input return loss, and output return loss not possible with conventional amplifier designs.
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