Method for fabricating semiconductor device with damascene structure

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United States of America

PATENT NO 12230535
APP PUB NO 20230307288A1
SERIAL NO

17701938

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Abstract

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The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack; and forming a via in the via opening and a trench in the trench opening. The translucent layer includes a mask opening of via feature which exposes a portion of the mask substrate. A thickness of the trench region is less than a thickness of the mask region.

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Patent Owner(s)

  • NANYA TECHNOLOGY CORPORATION

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  • 2022 Application Filing Year
  • H01L Class
  • 27731 Applications Filed
  • 8200 Patents Issued To-Date
  • 29.57 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances20222023202420250255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pan, Wei-Chen New Taipei, TW 12 3

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges12643501 - 1001000200030004000500060007000800090001000011000120001300014000

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