Semiconductor device, memory device, and electronic device
Number of patents in Portfolio can not be more than 2000
United States of America
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Feb 18, 2025
Grant Date -
Aug 10, 2023
app pub date -
Apr 18, 2023
filing date -
Apr 18, 2023
priority date (Note) -
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Abstract
A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.
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