Semiconductor memory device
Number of patents in Portfolio can not be more than 2000
United States of America
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Feb 18, 2025
Grant Date -
Mar 21, 2024
app pub date -
Nov 30, 2023
filing date -
Nov 30, 2023
priority date (Note) -
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Abstract
A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.
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