Apparatus and method for testing high-speed low-latency interconnect interface (HLII) for silicon interposer

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United States of America

PATENT NO 12229029
APP PUB NO 20230367683A1
SERIAL NO

18346892

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Abstract

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An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.

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Patent Owner(s)

  • WUXI ESIONTECH CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hu, Xiaochen Wuxi, CN 17 171
Ma, Xiaojie Wuxi, CN 6 2
Shan, Yueer Wuxi, CN 17 3
Xu, Yanfeng Wuxi, CN 20 12
Xu, Yuting Wuxi, CN 5 112
Zhang, Yanfei Wuxi, CN 22 7

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