Managing error-handling flows in memory devices

Number of patents in Portfolio can not be more than 2000

United States of America

PATENT NO 12229000
APP PUB NO 20230325273A1
SERIAL NO

18207525

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Abstract

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Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INC8000 SOUTH FEDERAL WAY BOISE ID 83716-9632

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Batutis, Devin M San Jose, US 18 21
Feeley, Peter Boise, US 167 1178
Kaynak, Mustafa N San Diego, US 162 465
Luo, Xiangang Fremont, US 119 201
Muchherla, Kishore Kumar San Jose, US 300 947
Nowell, Shane Boise, US 86 270
Parthasarathy, Sivagnanam Carlsbad, US 258 1182
Ratnam, Sampath K San Jose, US 158 775

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