Memory system using asymmetric source-synchronous clocking
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United States of America
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Feb 18, 2025
Grant Date -
Oct 17, 2024
app pub date -
Apr 8, 2024
filing date -
Apr 8, 2024
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Abstract
The disclosed embodiments relate to a memory system that generates a multiplied timing signal from a reference timing signal. During operation, the system receives a reference timing signal. Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time. Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant.
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