Clock and data recovery circuit using neural network circuit to obtain frequency difference information
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United States of America
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Feb 11, 2025
Grant Date -
Jan 4, 2024
app pub date -
Jan 30, 2023
filing date -
Jan 30, 2023
priority date (Note) -
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Abstract
The present invention includes a CDR circuit including a phase detector, a neural network circuit, a controller and a clock signal generator is disclosed. The phase detector is configured to use a clock signal to sample an input signal to generate a plurality of phase detection results. The neural network circuit is coupled to the phase detector, and is configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal. The controller is configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal. The clock signal generator is configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.
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