Apparatuses and methods of memory access control with section predecoding and section selection
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United States of America
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Feb 11, 2025
Grant Date -
Dec 14, 2023
app pub date -
Jun 14, 2022
filing date -
Jun 14, 2022
priority date (Note) -
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Abstract
Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.
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