CPUs with capture queues to save and restore intermediate results and out-of-order results

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United States of America

PATENT NO 12223327
APP PUB NO 20240036876A1
SERIAL NO

18487186

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Abstract

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Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

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Patent Owner(s)

  • TEXAS INSTRUMENTS INCORPORATED

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Anderson, Timothy D University Park, US 137 1170
Bui, Duc Grand Prairie, US 49 80
Tatge, Reid E Los Altos, US 17 233
Zbiciak, Joseph San Jose, US 131 676

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