Method of manufacturing integrated circuit having through-substrate via

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United States of America

PATENT NO 12223250
APP PUB NO 20230351086A1
SERIAL NO

18350738

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Abstract

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A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Ming-Fa Taichung, TW 524 4489
Chiang, Meng-Wei Hsinchu, TW 2 0
Hu, Chih-Chia Taipei, TW 52 329
Jan, Sen-Bor Tainan, TW 52 544

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