Multi-gate selector switches for memory cells and methods of forming the same
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United States of America
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Feb 4, 2025
Grant Date -
Dec 30, 2021
app pub date -
Apr 14, 2021
filing date -
Apr 14, 2021
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Abstract
A memory structure includes: first and second word lines; a high-k dielectric layer disposed on the first and second word lines; a channel layer disposed on the high-k dielectric layer and comprising a semiconductor material; first and second source electrodes electrically contacting the channel layer; a first drain electrode disposed on the channel layer between the first and second source electrodes; a memory cell electrically connected to the first drain electrode; and a bit line electrically connected to the memory cell.
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