Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies
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United States of America
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Feb 4, 2025
Grant Date -
May 23, 2024
app pub date -
Jan 31, 2024
filing date -
Jan 31, 2024
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Abstract
Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.
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