Wide voltage gate driver using low gate oxide transistors
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United States of America
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Feb 4, 2025
Grant Date -
Aug 3, 2023
app pub date -
Mar 24, 2023
filing date -
Mar 24, 2023
priority date (Note) -
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Abstract
A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.
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