Memory device with source line control
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United States of America
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Feb 4, 2025
Grant Date -
Nov 30, 2023
app pub date -
Aug 10, 2023
filing date -
Aug 10, 2023
priority date (Note) -
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Abstract
Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.
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