Processor circuit for generating ultrafast clock multiplier
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United States of America
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Feb 4, 2025
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N/A
app pub date -
Jan 11, 2024
filing date -
Jan 11, 2024
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Abstract
A photonic circuit for generating an ultrafast clock for a photonic processor. The photonic circuit includes a beam splitter, a phase shifter, a first photonic combiner coupled to the beam splitter and the phase shifter, and a second photonic combiner coupled to the beam splitter and the first photonic combiner. The beam splitter splits a received photonic seed clock signal into a first photonic seed clock signal and a second photonic seed clock signal. The phase shifter shifts a phase of a received photonic signal to generate a phase-shifted version of the photonic signal. The first photonic combiner combines the second photonic seed clock signal with the phase-shifted version of the photonic signal to generate a first combined photonic signal. The second photonic combiner combines a delayed and attenuated version of the first photonic seed clock signal with the first combined photonic signal to generate a photonic clock signal.
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