Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods
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United States of America
Stats
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Jan 28, 2025
Grant Date -
Aug 29, 2024
app pub date -
Feb 27, 2023
filing date -
Feb 27, 2023
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.
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International Classification(s)
- 2023 Application Filing Year
- H03L Class
- 302 Applications Filed
- 126 Patents Issued To-Date
- 41.73 % Issued To-Date
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- 0 Citation Count
- H03L Class
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